This invention relates to a method of producing a semiconductor device in which a hemispherical-grained (HSG'ed) capacitor electrode comprising a lower electrode of a silicon film, a dielectric film, and an upper electrode is formed on a semiconductor substrate and, in particular, to a method of producing a semiconductor device in which a hemispherical-grained (HSG'ed) capacitor electrode is heat-treated to introduce into hemispherical grains (HSGs) a dopant of a high concentration.
In a semiconductor device such as a DRAM (Dynamic Random Access Memory), it is generally required to form a capacitor electrode such as a stacked capacitor and a trench capacitor. For example, a capacitor electrode is formed in the following manner. At first, a polysilicon film is grown on a semiconductor substrate with an insulator film interposed therebetween. Then, an impurity such as phosphorus (P) is introduced into the polysilicon film. Thereafter, the polysilicon film is patterned by plasma etching using a photoresist film to form a lower electrode. After the surface of the lower electrode is coated with a dielectric film comprising an oxide film or a nitride film, an upper electrode is formed in the manner similar to the formation of the lower electrode. Herein, a combination of the lower electrode, the dielectric film, and the upper electrode forms the capacitor electrode.
There are various previous techniques relating to manufacture of the semiconductor device, such as the DRAM, having the capacitor electrode. For example, methods of producing semiconductor devices are disclosed in Japanese Unexamined Patent Publications (JP-A) Nos. 5-343614, 7-38062, and 9-289292.
In these previous techniques, formation of the capacitor electrode may or may not include a hemispherical-graining process (HSG process). In the capacitor electrode, the shape of the lower electrode on a capacitor contact formed in the semiconductor substrate of SiO.sub.2 is different depending upon whether or not the HSG process is carried out. Specifically, the HSG process produces a number of HSGs as mushroom-like protrusions on the surface of the lower electrode to thereby increase the surface area of the lower electrode. The surface area increased by the presence of the HSGs reaches about twice as compared with the case where no HSG process is performed. Therefore, the capacitor electrode subjected to the HSG process, which will hereafter be referred to as a hemispherical-grained (HSG'ed) capacitor electrode, has an ideal capacitance increased to about twice corresponding to the increase in surface area.
In recent years, there is a strong demand for a low heat-treatment temperature in a capacitor forming process because of a sophisticated device design. For example, in case of a 1GDRAM or a DRAM mounted together with a logic circuit, high-temperature heat treatment using a furnace is difficult to perform in the capacitor forming process. As the heat-treatment temperature becomes lower, the HSG'ed capacitor electrode suffers the reduction in capacitance due to depletion.
In the HSG'ed capacitor electrode, a capacitance versus voltage (C--V) characteristic representing the relationship between a capacitance and an applied voltage upon the upper electrode is such that, when a process temperature after formation of the HSGs is lowered, the decrease in capacitance is significant if the applied voltage upon the upper electrode has a negative value. This is because the interior of each HSG is depleted.
The reason why such depletion of the HSG is caused following the decrease in process temperature will presently be described. Specifically, immediately after the HSGs are formed in the HSG process, the interior of each HSG is a depletion region in a non-doped state. After the high-temperature heat treatment subsequently carried out, phosphorus is sufficiently diffused from a stack into each HSG so that the depletion region is lost. On the other hand, if doping is carried out only by the heat treatment at a low process temperature, diffusion of phosphorus into each HSG is insufficient so that the depletion region still remains. Due to the presence of the depletion region, the decrease in capacitance occurs when the applied voltage upon a plate electrode has a negative value.
In order to suppress the above-mentioned depletion, proposal is made of solid-phase diffusion of phosphorus using POCl.sub.3. Specifically, an HSG'ed wafer is heat-treated in a furnace with POCl.sub.3 contained therein. By doping using such phosphorus diffusion, SiO.sub.2 containing phosphorus at a high concentration is formed on the surface of each HSG. Therefore, phosphorus is introduced from SiO.sub.2 into the HSG so that a phosphorus diffusion region is formed.
However, in case of the hoping using the above-mentioned phosphorus diffusion, a PSG (Phospho Silicate Glass) film is formed by the use of oxidation of silicon in order to obtain SiO.sub.2 containing phosphorus. Therefore, each HSG is decreased in size after the diffusion as compared with that before the diffusion. As a result, the HSG is decreased in volume so that the surface area of the HSG is reduced. This makes it difficult to achieve a sufficient increase in capacitance. In addition, a base portion of each HSG becomes thin and is therefore reduced in mechanical strength.